1. Field of the Invention
The present invention relates to integrated circuit physical design automation. In particular, the present invention relates to an automated method and system for providing a physical design of an integrated circuit that is optimized for meeting power and interconnect-dominant timing requirements.
2. Discussion of the Related Art
Existing top-down design methods focus on optimizing transistors and gates, and model interconnect lines as merely "parasitic" elements of these transistors and gates. Implicit in this view of interconnect lines is the assumption that wiring delays and congestion in the interconnect lines are secondary to transistors and gates, and therefore can be taken into account as corrections to the timing and density models of the transistor and gates. As feature sizes of integrated circuits continue to shrink, this assumption is clearly no longer valid. In fact, interconnect is expected to dominate both performance and density in the near future.
FIG. 1 shows a typical existing design method 100. As shown in FIG. 1, an integrated circuit design is captured by a design entry step 101. Design entry step 101 is typically facilitated by a design capture system allowing the user to specify the logic design of the integrated circuit graphically, through a hardware description language (e.g., VHDL), or both. Typically, at design entry step 101, the user need not specify all elements of the design at the logic gate level. Many elements can be specified at a higher functional level (e.g., register-transfer level).
Upon completion of design entry step 101, a functional simulation step 102 is typically carried out using a functional simulator to verify functional behavior of the design. Based on a verified functional level description ("functional design"), the functional design can then be synthesized to the logic gate level in logic synthesis step 104, using a logic synthesis tool. Typically, at logic synthesis step 104, additional circuits for diagnostic and test purposes are included to provide a synthesized logic circuit ("gate-level design"). Such additional circuits may include, for example, test circuits for a boundary scan design under the JTAG standard.
Using the gate-level design, an initial circuit partitioning can be performed, i.e., floor planning step 103, to allow a first estimate of circuit size and to group highly connected portions of the design together to facilitate a subsequent layout step. In addition, a logic simulation (simulation step 109) and a static timing analysis (timing analysis step 108) are performed on the gate-level design to verify the gate-level design's functional behavior, and to extract estimates of timing parameters.
During this time, at formal verification step 107 and test structure verification step 106, the gate-level design is verified against both the functional design and a behavior description of the additional included circuits to ensure both the functional design's and the test structure's behaviors are preserved. Further, the gate-level design is also checked, at technology checking step 105, that technology-specific logic design rules are not violated.
The gate-level design, together with timing information from the static timing analysis, are integrated into a pre-layout design database in front-end processing step 110. At this time, a pre-layout signoff step 111 signifies the beginning of the physical realization phase of the integrated circuit design. FIG. 1 shows a layout step 112 in which the physical realization ("layout") is created by performing a number of tasks ("layout design tasks") iteratively.
Typically, layout design tasks include, generally, the steps of circuit partitioning, placement and routing. As mentioned above, an initial circuit partition based on the gate-level design is already provided at floor-planning step 103. Based on this initial partition, the circuit partitioning step in layout step 112 further refines circuit partitions down to the level of individual "cells" (e.g., logic gates or macro cells). These cells are then placed according to some constraints, which are typically expressed by a cost function. Typical constraints relate to area, power and local timing. The cells so placed are then routed to provide the necessary interconnect. The routing is also typically performed according to certain constraints, such as local timing and power constraints.
In the prior art, a final static timing analysis step 113 is then performed on the routed layout design, incorporating into the timing information delays introduced by the routing step. If final static timing analysis step 113 uncovers timing problems in some signal paths, an optimization cycle is initiated by flagging the gates along the problematic signal paths and returning the gate-level design back to logic synthesis step 104. In logic synthesis step 104, logic synthesis techniques are applied to improve the gate-level design in a revised gate-level design. Steps 105-113 are then repeated on the revised gate-level design. This optimization cycle is repeated until all timing problems are resolved, represented by the post-layout sign-off step 114. Test patterns can then be generated in an automatic test pattern generation (ATPG) step 116, and the final layout design can then be manufactured.
The existing top-down design methods not only suffer from the defective interconnect model mentioned above, but also from the long elapsed time between optimization cycles. With each optimization cycle, the logic synthesis, circuit partitioning, placement and routing are "point" tools, each operating on the entire design. Such loose coupling between tools in this optimization cycle is inefficient, since the steps towards convergence to an optimized layout tend to be small for each optimization cycle. For example, any possible improvement realizable by resynthesis of the logic circuit that arises because of a different placement of cells cannot be taken advantage of until the next optimization cycle. Furthermore, at the current and future circuit densities, the amount of CPU cycles used in each point tool in the optimization cycle is enormous, with many cycles expended in repeating tasks also performed in the previous optimization cycles. Further, since each existing point tool is typically acquired from a different vendor, there is substantial inefficiency in the interface between point tools. Typically, each point tool reads into memory a large data file provided by an upstream point tool, and provides its results in another large data file to be read by a downstream point tool.
The long optimization cycles can be alleviated somewhat by the use of parallel point tools. An example of such a parallel point tool is disclosed in U.S. Pat. No. 5,495,419 to Rostoker et al., entitled "INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATIC SYSTEM UTILIZING OPTIMIZATION PROCESS DECOMPOSITION AND PARALLEL PROCESSING," issued Feb. 27, 1996. In Rostoker et al, a parallel placement algorithm is executed by parallel processors, thereby shortening the time to achieve the placement function.
Thus, a method is desired for optimizing the integrated circuit design process, which both takes advantage of parallel algorithms and closely couples the layout design tasks in the optimization cycle is desired.